![[ICO]](/icons/blank.gif) | Name | Last modified | Size | Description |
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![[PARENTDIR]](/icons/back.gif) | Parent Directory | | - | |
![[ ]](/icons/unknown.gif) | T flip-flop with preset (TFFP).ssc | 2025-07-08 14:05 | 4.8K | |
![[ ]](/icons/unknown.gif) | Full-adder (FA).ssc | 2025-07-08 14:05 | 4.5K | |
![[ ]](/icons/unknown.gif) | Divider FSM control logic (DIVFSM).ssc | 2025-07-08 14:05 | 19K | |
![[ ]](/icons/unknown.gif) | D flip-flop with clear and preset (DFFCP).ssc | 2025-07-08 14:05 | 7.1K | |
![[ ]](/icons/unknown.gif) | Delay (DLY).ssc | 2025-07-08 14:05 | 2.1K | |
![[ ]](/icons/unknown.gif) | 8-bit synchronous up-counter with enable (CNTR8).ssc | 2025-07-08 14:05 | 12K | |
![[ ]](/icons/unknown.gif) | 8-bit shift register (SHIFT8).ssc | 2025-07-08 14:05 | 24K | |
![[ ]](/icons/unknown.gif) | 8-bit select or clear (SELCLR8).ssc | 2025-07-08 14:05 | 8.5K | |
![[ ]](/icons/unknown.gif) | 8-bit register (REG8).ssc | 2025-07-08 14:05 | 10K | |
![[ ]](/icons/unknown.gif) | 8-bit divider test circuit.ssc | 2025-07-08 14:05 | 21K | |
![[ ]](/icons/unknown.gif) | 8-bit divider circuit.ssp | 2025-07-08 14:05 | 914 | |
![[ ]](/icons/unknown.gif) | 8-bit divider (DIV8).ssc | 2025-07-08 14:05 | 29K | |
![[ ]](/icons/unknown.gif) | 8-bit adder (ADD8).ssc | 2025-07-08 14:05 | 12K | |
![[ ]](/icons/unknown.gif) | 3-bit down-counter with load (DCNT3L).ssc | 2025-07-08 14:05 | 5.6K | |
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