Index of /dokumenti/SmartSim/division_b

	Name	Last modified	Size	Description
	Parent Directory		-
	8-bit divider circuit.ssp	2024-12-14 05:23	914
	Delay (DLY).ssc	2024-12-14 05:23	2.1K
	Full-adder (FA).ssc	2024-12-14 05:23	4.5K
	T flip-flop with preset (TFFP).ssc	2024-12-14 05:23	4.8K
	3-bit down-counter with load (DCNT3L).ssc	2024-12-14 05:23	5.6K
	D flip-flop with clear and preset (DFFCP).ssc	2024-12-14 05:23	7.1K
	8-bit select or clear (SELCLR8).ssc	2024-12-14 05:23	8.5K
	8-bit register (REG8).ssc	2024-12-14 05:23	10K
	8-bit adder (ADD8).ssc	2024-12-14 05:23	12K
	8-bit synchronous up-counter with enable (CNTR8).ssc	2024-12-14 05:23	12K
	Divider FSM control logic (DIVFSM).ssc	2024-12-14 05:23	19K
	8-bit divider test circuit.ssc	2024-12-14 05:23	21K
	8-bit shift register (SHIFT8).ssc	2024-12-14 05:23	24K
	8-bit divider (DIV8).ssc	2024-12-14 05:23	29K