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| Name | Last modified | Size | Description |
|---|---|---|---|---|
| Parent Directory | - | ||
| 16 bit 2 to 1.ssc | 2025-08-13 12:11 | 22K | |
| 16 bit addition using full adder.ssc | 2025-08-13 12:11 | 22K | |
| 16 bit bidirectional controller.ssc | 2025-08-13 12:11 | 24K | |
| 16 bit d flipflop array.ssc | 2025-08-13 12:11 | 17K | |
| 16 bit tristate.ssc | 2025-08-13 12:11 | 16K | |
| 16 state selector.ssc | 2025-08-13 12:11 | 23K | |
| bidirectional controller.ssc | 2025-08-13 12:11 | 2.4K | |
| computer.ssc | 2025-08-13 12:11 | 12K | |
| delay 2.ssc | 2025-08-13 12:11 | 1.3K | |
| full adder.ssc | 2025-08-13 12:11 | 4.1K | |
| half adder.ssc | 2025-08-13 12:11 | 2.3K | |
| memory controller.ssc | 2025-08-13 12:11 | 48K | |
| memory controller fsm.ssc | 2025-08-13 12:11 | 9.6K | |
| processor.ssc | 2025-08-13 12:11 | 101K | |
| processor fsm.ssc | 2025-08-13 12:11 | 11K | |
| programs/ | 2025-08-13 12:11 | - | |
| readme.txt | 2025-08-13 12:11 | 593 | |
| sbn oisc.ssp | 2025-08-13 12:11 | 955 | |
| state selector bit.ssc | 2025-08-13 12:11 | 3.0K | |
| up set counter 16.ssc | 2025-08-13 12:11 | 32K | |